DC-to-DC controller having a multi-phase synchronous buck regulator

ABSTRACT

A DC-to-DC regulator that includes a multi-phase synchronous buck regulator having a pulse width modulator to generate a plurality of switching signals, a plurality of drivers, each coupled to receive one of the switching signals, and a plurality of switching voltage converters, each coupled to receive an output from one of the drivers and an input voltage, wherein the outputs of the switching voltage converters are combined to form an output voltage. The multi-phase synchronous buck regulator can be implemented on a motherboard, such as on an interposer board or directly on a PU chip.

FIELD

The invention generally relates to voltage regulators and in particularto multi-phase pulse width modulated (PWM) direct-current (DC) to DCvoltage regulators.

BACKGROUND

Most electronic circuits, from simple transistors and op-amp circuits upto elaborate digital and microprocessor systems, require one or moresources of stable DC voltage. DC-to-DC converters are well-known in theart. Such circuitry or devices are typically employed to convert fromone DC voltage signal level to another DC voltage signal level. This maybe useful in a variety of environments.

Today's sophisticated processing units (PUs) have made the job of thepower supply designer more difficult. These PUs continue to demand everyhigher currents and lower voltages. One problem is providing a desired,highly regulated, voltage which may vary in a range, such as, forexample, from 0.96 volts to 1.04 volts, and that may depend, at least inpart, on clock speed. Another challenge is to provide this voltage atrelatively high currents that may vary from several hundred milliamps,up to, for example, 120 amps, and back again, in a clock cycle, forexample. Furthermore, yet a third challenge is to provide a scalabledesign that meets these higher current requirements by using multipleinstances of a common building block connected together in parallel.Therefore, a need exists for a DC-to-DC regulator circuit that is atleast closer to accomplishing these objectives, or at least one of them,than state-of-the-art circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and a better understanding of the present invention willbecome apparent from the following detailed description of exampleembodiments and the claims when read in connection with the accompanyingdrawings, all forming a part of the disclosure of this invention. In thedrawings, like reference numbers generally indicate identical,functionally similar, and/or structurally similar elements. While theforegoing and following written and illustrated disclosure focuses ondisclosing example embodiments of the invention, it should be clearlyunderstood that the same is by way of illustration and example only andthe invention is not limited thereto. The spirit and scope of thepresent invention are limited only by the terms of the appended claims.

The following represents brief descriptions of the drawings, wherein:

FIG. 1 is a block diagram illustrating a multi-phase synchronous buckregulator implemented on a motherboard according to an exampleembodiment of the present invention;

FIG. 2 is a block diagram illustrating the multi-phase synchronous buckregulator in greater detail according to an example embodiment of thecurrent invention;

FIG. 3 represents an overall circuit layout for combining the circuitparts of FIGS. 3A-3F, such circuit illustrating a four-phase synchronousbuck regulator according to an example embodiment of the presentinvention, where the regulator is implemented on a PU;

FIG. 4 represents an overall circuit layout for combining the circuitparts of FIGS. 4A-4D, such circuit illustrating a four-phase synchronousbuck regulator according to an example embodiment of the presentinvention, where the regulator is implemented on an interposer; and

FIGS. 5A and 5B are circuit diagrams illustrating a first and secondover-voltage protection circuit according to example embodiments of thepresent invention.

DETAILED DESCRIPTION

Before beginning a detailed description of the subject invention,mention of the following is in order. When appropriate, like referencenumerals and characters may be used to designate identical,corresponding or similar components in differing figure drawings.Further, in the detailed description to follow, examplesizes/models/values/ranges may be given, although the present inventionis not limited to the same. Well known power/ground connections tointegrated circuits (ICs) and other components may not be shown withinthe figures for simplicity of illustration and discussion, and so as notto obscure the invention. Further, arrangements may be shown in blockdiagram form in order to avoid obscuring the invention, and also in viewof the fact that specifics with respect to implementation of such blockdiagram arrangements is highly dependent upon the platform within whichthe present invention is to be implemented, i.e., specifics should bewell within purview of one skilled in the art. Where specific details(e.g., circuit diagrams) are set forth in order to describe exampleembodiments of the invention, it should be apparent to one skilled inthe art that the invention can be practiced without these specificdetails.

Reference in the specification to “one example embodiment”0 or “anexample embodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the invention. The appearance of the phase“in one example embodiment” in various places in the specification arenot necessarily all referring to the same embodiment.

An example embodiment of the present invention is directed to a DC-to-DCregulator that includes a multi-phase synchronous buck regulator havinga pulse width modulator to generate a plurality of switching signals, aplurality of drivers, each coupled to receive one of the switchingsignals, and a plurality of switching voltage converters, each coupledto receive an output from one of the drivers and an input voltage,wherein the outputs of the switching voltage converters are combined toform an output voltage. The multi-phase synchronous buck regulator canbe implemented on a motherboard, such as on an interposer board ordirectly on a PU chip.

FIG. 1 is a block diagram illustrating a multi-phase synchronous buckregulator 130 implemented on a computer motherboard 108 according to anexample embodiment of the present invention. An alternating current (AC)wall socket 102 provides an AC current to a power supply 104. Powersupply 104 converts the AC signal into one or more DC voltages (wherethe number of DC voltages is given by N). For example, power supply 104can convert the AC signal into two DC voltages, 12 volts and 5 volts. Adistribution board 106 distributes the DC voltages to various loads,including regulator 130. Distribution board 106 provides a lowimpedance, low inductance path to the load (e.g., memory, chip sets,PU).

Regulator 130 is implemented on a motherboard 108 (sometimesalternatively referred to, for example, as a processor host board).Motherboard 108 includes an interposer 122 that plugs into a processorsocket 120, one or more Organic LAN Grid Arrays (OLGAs) 124 (shown as124A and 124B), and one or more PUs 126. Regulator 130 converts the oneor more input DC voltages received from distribution board 106 to anoutput voltage that is used by PU 126. Regulator 130 therefore providesthe complex, highly regulated voltages required by PU 126. Regulator 130converts any of the N input DC voltages to an output DC voltage that canrange, for example, from 0.9 volts to 1.6 volts, depending on the clockspeed of PU 126. Acceptable tolerances in the output voltage signal areoften expressed as a percentage of the mean output voltage. According toan example embodiment of the present invention, regulator 130 providesan output voltage of 1 volt±4% (i.e., the output voltage can range from0.96 volts to 1.04 volts). Further, regulator 130 provides an outputvoltage even where the current load varies from 0 amps (e.g., where PU126 is in stand-by) to 200 amps and above, and back again in a singleclock cycle.

Prior voltage regulators were implemented on a card separate frommotherboard 108. These voltage regulator cards were therefore pluggedinto a socket separate from the processor socket. These plug-in voltageregulators require that many decoupling capacitors be implemented onmotherboard 108, interposer 122, and OLGA 124 to handle the dynamicresponse requirements of PU 126. Decoupling capacitors require asignificant amount of real estate on motherboard 108, increase cost,block air flow through the system and contribute to system heating.Further, the distributed impedance associated with the distribution andinterconnect between the plug-in voltage regulator and motherboard 108limits the performance of plug-in voltage regulators.

According to the present invention, regulator 130 is implemented onmotherboard 108, rather than as a separate plug-in module, minimizingthe distributed impedance between regulator 130 and PU 126. According toan example embodiment, as depicted in FIG. 1, regulator 130 can beimplemented on interposer board 122. In this first example embodiment,regulator 130 can provide an output DC voltage to one or more PUs 126.According to another example embodiment, regulator 130 can alternativelybe implemented directly on PU 126. In this second example embodiment,regulator 130 provides an output DC voltage to the PU on which regulator130 is implemented. These example embodiments are described in greaterdetail below.

According to an example embodiment of the present invention, regulator130 is implemented using surface mount technology (SMT) output inductorsand capacitors, and a number of low inductance, low capacitance, lowon-resistance surface mount packages 8-pin package (S08). As a result,the dynamic response of regulator 130 is greatly improved due to its lowoutput impedance path. The number of required output capacitors withinregulator 130 is reduced, freeing up more space on interposer 122.

FIG. 2 is a block diagram illustrating an M-phase synchronous buckregulator 130 in greater detail according to an example embodiment ofthe current invention, where M is the number of phase in the multi-phaseregulator. Regulator 130 includes a pulse width modulator 204, asequence timing control 206, a number of drivers 208 equal to the numberof phases (shown as 208-1 through 208-M), a similar number of switchingvoltage converters 210 (shown as 210-1 through 210-M), and a regulationcircuit 214. The input DC voltages 202 (shown as 202-1 through 202-N)from power supply 104 are input to regulator 130. Regulator 130 convertsinput voltages 202 to an output voltage 212.

Pulse width modulator 204 generates a number of switching signals 220equal to the number of phases M (shown as 220-1 to 220-M). The switchingsignals may be square-wave in shape, and are out of phase from oneanother. For example, with a four-phase regulator, pulse width modulator204 generates four switching signals, where the signals from one phaseto the next are separated by 90°. For each of the M phases, theswitching signal power is boosted by driver 208 (the boosted signals aredepicted by lines 224-1 through 224-M). Driver 208 provides the powernecessary to drive switching voltage converter 210 at a high frequency.

Sequence timing control 206 insures that regulator 130 will operateproperly regardless of the sequencing of input DC voltages 202. Priorvoltage regulators required that, whenever multiple input DC voltageswere allowed, they were required to follow a particular preset temporalpattern. For example, a prior voltage regulator that received as input a12 volt and a 5 volt DC signal, the prior voltage regulator mightrequire that the 12 volt and 5 volt signals alternate over time.Deviation from this pattern could potentially result in catastrophicfailure for the voltage regulator. Requiring a known pattern ofsequencing requires a more complex and expensive system. According tothe present invention, sequencing timing control 206 allows the input DCvoltages to come up or down at random, in any sequence, by insuring thatdrivers 208 turn on before pulse width modulator 204.

According to an example embodiment of the present invention, switchingvoltage converter 210 represents a pulse width modulated (PWM)series-switch step-down converter. PWM converters an be used to obtain alower voltage from a higher one by using a low-impedance transistorswitch that is made to open and close periodically between input andoutput. The transistor switch is driven by the switching voltagegenerated by pulse width modulator 204. As is well known in the art, anydesired output voltage lower than the input voltage can be obtained byvarying the width of the “on” time switching signal. Exampleimplementations of switching voltage converter 210 are described ingreater detail below.

Output voltage 212 is formed by combining the outputs of the switchingvoltage converters 210. The output capacitance of regulator 130 causes aripple on output voltage 212. The output can be modeled as a capacitancein series with an inductance and a resistance. Even under steady-stateconditions, the capacitor will charge and then discharge, causing theoutput ripple. One advantage of the present invention is that the ripplecomponents from each phase cancel one another, which can reduce thetotal output ripple by a factor of 10 or more.

Further, regulation circuit 214 provides the feedback necessary forvoltage regulation. The particular implementation of regulation circuit214 can vary according to whether a voltage mode topology or a currentmode topology is used. Example embodiments of regulation circuit 214 aredescribed in greater detail below.

FIG. 3 represents an overall circuit layout for combining the circuitparts of FIGS. 3A-3F, such circuit illustrating a four-phase synchronousbuck regulator 130A according to an example embodiment of the presentinvention, where regulator 130A is implemented on PU 126.Interconnectable arrow heads (“>>”) are used to designate conductionpaths which should be reconnected between the various circuit parts,while a smaller number of reconnectable conduction paths have beenmarked with matching encircled letters in neighboring circuit parts tohelp index and align the conduction paths which should be reconnected. Aremainder of this disclosure should be taken as referring to the overallcircuit in its assembled form, and the terminology “FIG. 3” mayhereinafter be used to refer to the assembled overall circuit. Regulator130A receives input DC voltage 202-1 (+12 volts for the example shown inFIG. 3) and input DC voltage 202-2 (+5.6 volts for the examples shown inFIG. 3). The output voltage 212 terminal appears on the right-hand sideof the overall figure. Example regulator 130A can provide, for example,60 amps of current to PU 126.

According to an example embodiment of the present invention, regulator130A is implemented around a perimeter of a PU 126 chip. Also, thermalvias and a multiple layer copper plane are used to equally and quicklydissipate heat from the switching MOSFETs (within switching voltageconverters 210) to the open air. As a result, heat sinks are notrequired for dissipating heat from the switching MOSFETs.

Pulse width modulator 204 can be implemented, for example, usingSemtech's programmable, multi-phase, high performance PWM controllerSC1146, and the supporting circuitry shown in FIG. 3. The four switchingsignals 222 generated by the SC1146 are shown as pins Drv0 through Drv3.

The example sequence timing control circuit 206 depicted in FIG. 3includes resistors R46 and R48, capacitors C42 and C44, and diodes D11A,D11B, D12A, D12B, and D13A, configured as shown in FIG. 3. Examplevalues for the resistors and capacitors included within this examplesequence timing control circuit 206 are shown in FIG. 3. The diodeswithin this example sequence timing control circuit 206 can beimplemented using Phillip Electronics' diodes BAW56. For exampleregulator 130A, the example sequence timing control circuit depicted inFIG. 3 insures that regulator 130A operates correctly regardless of thesequence of input voltages 202-1 and 202-2.

Each of the four drivers 208 can be implemented, for example, usingSEMTECH's high speed synchronous power MOSFET smart driver SC1405, andthe supporting circuitry shown in FIG. 3. Each driver 208 receives aswitching signal 222 generated by pulse width modulator 204, and outputsthe boosted signal at the pin labeled TG.

Switching voltage converters 210 are each implemented using similarparts. For example, switching voltage converters 210-1 includes diodeD3, capacitors C19, C20, and C23, resistors R20, R21, and R22, MOSFETsQ1 and Q2, and inductor L1, configured as shown in FIG. 3. Examplevalues for the resistors, capacitors, and inductor included within theseexample switching voltage converters 210 are shown in FIG. 3. The diodeswithin these example switching voltage converters 210 can be implementedusing MOTOROLA diodes MBRA13OLT3. The MOSFETs Q1 and Q2 can beimplemented using INTERNATIONAL RECTIFIER'S MOSFETs IRF7809/IRF7811. Theinductor L1 can be implemented using VISHAY's inductor IHLP 5050FD-01.

Note that many of the component depicted in FIG. 3 have a “x” followedby a number in close proximity to the component symbol. This indicatesthat the component is implemented using the stated number of duplicatecomponents connected in parallel. For example, “x2” appears just abovethe label for capacitor C40. This indicates that C40 represents twocapacitors, each having a value of 1 μF, connected in parallel.

The outputs of switching voltage converters 210-1 through 210-4 are tiedtogether to form output voltage 212. FIG. 3 depicts an example outputcapacitance given by capacitors C10, C11, C39, and C40.

The example regulation circuit 214 depicted in FIG. 3 includes resistorsR69, R70, R73, R29, and R63. The positive terminal of output voltage 212is fed back to pin FB 14, whereas the negative terminal is fed back topin FBG 16. The example regulation circuit 214 also includes analternative feedback path indicated by VoSen(+) and VoSen(−), wherethese terminals represent remote sensing.

According to the example embodiment of the present invention, regulator130A can also include a droop circuit, an example of which is shown inFIG. 3. This example droop circuit includes resistors R43, R49, R50,R53, R54, R59, R55, and R56, capacitor C47, op-amp U3A, and N-channeltransistor Q10, configured as shown in FIG. 3. Example values for theresistors and the capacitor included within this example droop circuitare shown in FIG. 3. Op-amp U3A can be implemented, for example, usingTEXAS INSTRUMENTS co-amp TL072. N-channel transistor Q10 can beimplemented, for example, using MOTOROLA's NPN transistor MMBT3904.

As described above, output voltage 212 for many applications must staywithin a well defined range of acceptable values. In the example givenabove, output voltage 212 can vary from 0.96 volts to 1.85 volts, where1.6 volts is the mean steady state output voltage, otherwise referred toherein as the voltage identification (V_(ID)) setting. However, thecurrent requirements of PU 126 vary over time. For example, PU 126 cango from a stand-by mode, requiring from zero to a few hundred milliamps,to a power-on mode requiring 100 amps and above, and back to stand-bymode, all in the span of a single clock cycle. The step-up transition inthe current load (i.e., from stand-by to power-on modes) causes atransitory dip in output voltage 212. Conversely, the step-downtransition in the current load (i.e., from power-on to stand-by modes)causes a transitory spike in output voltage 212. In order to maintainproper operation, regulator 130 should insure that output voltage 212remains within the defined range of acceptable values, even during dipsand spikes due to step-up and step-down transitions. The magnitude ofthe dips and spikes can be lessened by adding additional outputcapacitance.

The droop circuit allows the circuit designer to program the V_(ID)setting of output voltage 212. For the example droop circuit shown inFIG. 3, the V_(ID) setting is programmed by selecting particular valuesfor resistors R55 and R56. For example, the values shown for resistorsR55 and R56 result in a droop voltage of 40 millivolts, i.e., the outputvoltage 212 is increased by 40 millivolts. This makes better use of theavailable range of output voltage because magnitude of the dip caused bythe step-up transition is often larger than the magnitude of the spikecaused by the step-down transition. In other words, by increasing theV_(ID) setting, dips due to the step-up transition are less likely tocross the lower acceptable boundary of output voltage 212. And becausethe spikes due to step-up transitions are lower in magnitude relative tothe dips, increasing the V_(ID) setting may not result in increasedviolations of the upper acceptable boundary of output voltage 212.

By adding droop voltage to increase the V_(ID) setting, the number ofcapacitors that are required to control the magnitude of the step-uptransition dips can be reduced. For example, where output voltage 212 isconstrained to 1 volt±4%, adding a 40 millivolt droop reduces the amountof capacitance by 25 percent.

Further, the example droop circuit shown in FIG. 3 has the additionaladvantage of being very fast, which means that the droop circuit canrespond quickly to AC transient load events and can provide the 40millivolt drop voltage to the circuit. This increased speed results inbetter dynamic performance for regulator 130A.

According to the example embodiment of the present invention, regulator130A can also include a current sharing circuit, an example of which isshown in FIG. 3. This example current sharing circuit includes resistorsR60, R62, and R68, capacitor C48, op-amp U3B, and diode D14A, configureds shown in FIG. 3. Example values for the resistors and the capacitorincluded within this example current sharing circuit are shown in FIG.3. Op-amp U3B can be implemented, for example, using TEXAS INSTRUMENTSco-amp TL072. Diode D14A can be implemented, for example, using PHILLIPSELECTRONICS diode BAW56.

The current sharing circuit insures that the current load is distributedevenly between multiple regulators 130A that are connected together inparallel. The current sharing circuit therefore makes regulator 130Ascalable in the sense that multiple regulator modules can be combined tosatisfy larger current requirements. Without the current sharingcircuit, there is no guarantee that each regulator module will carry anequal portion of the total current load. This can result in particularmodules carrying a load greater than they are designed for, which candamage the module.

According to the example embodiment of the present invention, regulator130A can also include an over-voltage protection circuit, an example ofwhich is shown in FIG. 5A. The overvoltage protection circuit monitorsoutput voltage 212, and halts operation of regulator 130A if the outputvoltage crosses a certain threshold. This example over-voltageprotection circuit includes resistors R33, R34, R35, and R37, capacitorsC37 and C38, reference Zener diode U2 and a synchronous controlledrectifier SCR1, and P-channel transistor Q9, configured as shown in FIG.5A. Example values for the resistors and capacitors included within thisexample overvoltage protection circuit are shown in FIG. 5A. ReferenceZener diode U2 can be implemented, for example, using Texas Instrumentsreference regulator TL431. Synchronous controlled rectifier SCR1 can beimplemented, for example, using Motorola rectifier 2N6504. P-channeltransistor Q9 can be implemented, for example, using Motorola P-channeltransistor MMBT3906. The output voltage threshold is 2.098 volts for theexample over-voltage protection circuit depicted in FIG. 5A.

Very high frequency switching signals 220 can be achieved using thedesign of regulator 130A according to the present invention. Priorregulators have achieved switching frequencies of approximately 250 kHzper phase (total of 1 MHz for a four phase design). Regulator 130A canachieve at least a 1-2 MHz switching rate per phase (total of 4-8 MHz).This increased switching frequency is due, in part, to several factors:(i) the selection of fast drivers 208 with low output impedance and lowinput capacitance MOSFETs within switching voltage converter 210, (ii)the decreased loop inductance (and therefore increased speed) resultingfrom moving regulator 130A onto PU 126, and (iii) the selection of highQ and low resistance output inductors within switching voltage converter210. The output inductors should be very small and very efficient inorder to support the high switching rate of regulator 130A.

Switching at high frequencies results in many benefits for regulator130A. As PU 126 power requirements increase, regulator 130A must eitherswitch faster or use larger components. Faster switching means thatsmaller capacitors can be used at the output of regulator 130A, savingchip real estate and costs associated with the additional capacitivecomponents. Also, regulator 130A can respond more quickly to step-up andstep-down transitions by PU 126. Faster switching reduces the voltagedip associated with the step-up transitions. Another advantage is thatregulator 130A can be implemented using surface mount technology (SMT)rather than through-hole technology which is bulky and more difficult tomanufacture.

In another example embodiment, the components within an area 1000 inFIG. 3E may be able to be omitted. Further, throughout the drawingpertaining to example circuits, any component having a designation “DNS”associated therewith may be omitted.

FIG. 4 represents an overall circuit layout for combining the circuitparts of FIGS. 4A-D, such circuit illustrating a four-phase synchronousbuck regulator 130B according to another example embodiment of thepresent invention, where regulator 130B is implemented on interposer122. Again, just like with FIG. 3, interconnectable arrow heads andindexing encircled letters are used with respect to reconnectableconduction paths, and the terminology “FIG. 4” will hereinafter be usedto refer to the assembled overall circuit. Regulator 130B receives inputDC voltage 202-1 (+12 volts for the example shown in FIG. 4) and inputDC voltage 202-2 (+5.0 volts for the example shown in FIG. 4). Theoutput voltage 212 terminal appears on the right-hand side of FIG. 4.

According to an example embodiment of the present invention, regulator130B can provide output voltage 212 to multiple PUs 126 resident onmotherboard 108. The example regulator 130B depicted in FIG. 4 isdesigned to supply a total of 120 amps of current to two PUs 126. Thoseskilled in the art will recognize that the design of regulator 130B caneasily be extended to support more than two PUs 126.

According to the example regulator 130B embodiment, pulse width modular204 can be implemented, for example, using INTERSIL's PWM controllerHIP6301, in addition to the supporting circuitry shown in FIG. 4. TheHIP6301 has a built-in droop circuit, which operates in a manner similarto the droop circuit described above with respect to FIG. 3.

The example sequence timing control circuit 206 depicted in FIG. 4includes resistors R198 and R223, capacitor C101, and diode CR18,configured as shown in FIG. 4. This example sequence timing controlcircuit operates in a manner similar to that described above withrespect to the example sequence timing control circuit depicted in FIG.3. Example values are shown in FIG. 4 for the resistors and capacitorincluded within this example sequence timing control circuit 206. DiodeCR18 can be implemented, for example, using MOTOROLA diode IN4148.

The four drivers 208 can be implemented as described above with respectto FIG. 3, for example, using SEMTECH's high speed synchronous MOSFETsmart driver SC1405, and the supporting circuitry shown in FIG. 4. Theswitching voltage converter 210 within each phase are each implementedusing similar parts. For example, switching voltage converter 210-1 asshown in FIG. 4 includes diode CR3, capacitors C77, C94, Cd, and C227,resistors R37, R39, R77, R217, R52, and R106, in MOSFETs Q15 and Q21,and inductor L5, configured as shown in FIG. 4. Example values for theresistors, capacitors, and inductor included within these exampleswitching voltage converters 210 are shown in FIG. 4. The diodes withinthese example switching voltage converters 210 can be implemented usingMOTOROLA diodes MBRA130LT3. The MOSFETs switches can be implementedusing INTERNATIONAL RECTIFIER's MOSFETs IRF7809/IRF7811. The inductorscan be implemented using Vishay's inductor IHLP5050FD-01.

The outputs of switching voltage converters 210-1 through 210-4 are tiedtogether to form output voltage 212. FIG. 4 depicts an example outputcapacitance given by capacitors Ci, Cj, Ck, and Cl.

The example regulation circuit 214 depicted in FIG. 4 differs from theregulation circuit described above with respect to FIG. 3 in thatregulator 130B is implemented using a current mode topology, whereasregulator 130A is implemented using a voltage mode topology. Currentmode topologies require both voltage and current feedback, where voltagemode topologies require only voltage feedback. As shown in FIG. 4,voltage feedback is achieved by connecting output voltage 212 to theVsen pin on the HIP6301 via a resistor R222. Current feedback isachieved by feeding back a current signal from each phase, shown asIsen1 through Isen4, to the Isen1 through Isen4 pins on the HIP6301.

Though no current sharing circuit is shown in FIG. 3, such a circuitcould be added to regulator 130A in a manner similar to that describedabove with respect to regulator 130B. Adding a current sharing circuitwould make regulator 130A scalable in the sense that multiple regulatormodules could then be connected in parallel to support larger currentloads.

According to the example embodiment of the present invention, regulator103B can also include an over-voltage protection circuit, an example ofwhich is shown in FIG. 5B. The over-voltage protection circuit operatesin a manner similar to the circuit described above with respect to FIG.5A. This example over-voltage protection circuit includes resistorsR160, R161, R162, R163, and R164, capacitors C299 and C303, a referenceZener diode U59 and synchronous controlled rectifier SC26, and aP-channel transistor Q25, configured as shown in FIG. 5B. Example valuesfor the resistors and capacitors included within this exampleover-voltage protection circuit are shown in FIG. 5B. Reference Zenerdiode U59 can be implemented, for example, using TEXAS INSTRUMENTSregulator TL431. Synchronous controlled rectifier SC26 can beimplemented, for example, using MOTOROLA rectifier 2N6504. P-channeltransistor Q25 can be implemented, for example, using any P-channeltransistor MMBT3906.

Although the present invention has been described with reference to anumber of illustrative embodiments thereof, it should be understood thatnumerous other modifications and embodiments can be devised by thoseskilled in the art that will fall within the spirit and scope of theprinciples of this invention. More particularly, reasonable variationsand modifications are possible in the component parts and/orarrangements of the subject combination arrangement within the scope ofthe foregoing disclosure, the drawings and the appended claims withoutdeparting from the spirit of the invention. In addition to variationsand modifications in the component parts and/or arrangements,alternative uses will also be apparent to those skilled in the art.

For example, while the above example discussions describe sequencetiming control 206 and drivers 208 as being implemented using separateparts, the sequence timing control may instead be implemented withindrivers 208 rather than as a separate circuit. For example, SEMTECH'smulti-phase current mode controller with I-share bus SC2424 includes abuilt-in sequence timing control circuit that operates in a mannersimilar to that described above with respect to FIGS. 3 and 4.

What is claimed is:
 1. A DC-to-DC regulator, comprising: a multi-phasesynchronous buck regulator including: a pulse width modulator togenerate a plurality of switching signals, at least one of saidswitching signals being out-of-phase with respect to other ones of saidswitching signal signals, a plurality of drivers, each coupled toreceive one of said switching signals, and a plurality of switchingvoltage converters, each coupled to receive an output from one of saiddrivers and an input voltage, wherein the outputs of said switchingvoltage converters are combined to form an output voltage, and whereinsaid multi-phase synchronous buck regulator is implemented on amotherboard.
 2. The DC-to-DC regulator of claim 1, further comprising adroop circuit to add a droop voltage to said output voltage.
 3. TheDC-to-DC regulator of claim 2, wherein said multi-phase synchronous buckregulator is coupled to receive a plurality of input voltages, andwherein said multi-phase synchronous buck regulator further comprises asequence timing control circuit to allow proper operation of saidmulti-phase synchronous buck regulator regardless of the sequencing ofsaid input voltages.
 4. The DC-to-DC regulator of claim 1, wherein saidmulti-phase synchronous buck regulator further comprises an over-voltageprotection circuit.
 5. The DC-to-DC regulator of claim 1, wherein saidmulti-phase synchronous buck regulator is implemented on a centralprocessing unit chip.
 6. The DC-to-DC regulator of claim 5, wherein saidpulse width modulator comprises a programmable, multi-phase highperformance PWM controller.
 7. The DC-to-DC regulator of claim 6,wherein each of said drivers comprises a high speed synchronous powerMOSFET smart driver.
 8. The DC-to-DC regulator of claim 7, wherein eachof said switching voltage converters includes a plurality of switchingMOSFETs, and an output inductor.
 9. The DC-to-DC regulator of claim 1,wherein said multi-phase synchronous buck regulator is implemented on aninterposer.
 10. The DC-to-DC regulator of claim 9, wherein said pulsewidth modulator comprises a PWM controller.
 11. The DC-to-DC regulatorof claim 1, wherein the switching signal from one phase to a next phaseare separated by 90°.
 12. A DC-to-DC regulator, comprising: a pluralityof multi-phase synchronous buck regulator modules, wherein each of saidmodules includes: a pulse width modulator to generate a plurality ofswitching signals, at least one of said switching signals beingout-of-phase with respect to other ones of said switching signals. aplurality of drivers, each coupled to receive one of said switchingsignals. a plurality of switching voltage converters, each coupled toreceive an output from one of said drivers and an input voltage, whereinthe outputs of said switching voltage converters are combined to form anoutput voltage, and a current sharing circuit to insure that the currentload is shared amongst said plurality of multi-phase synchronous buckregulator modules, and wherein said multi-phase synchronous buckregulator modules are implementedon a motherboard.
 13. The DC-to-DCregulator of claim 11, wherein the switching signals from one phase to anext phase are separated by 90°.
 14. A system comprising a DC-to-DCregulator comprising: a multi-phase synchronous buck regulatorincluding: a pulse width modulator to generate a plurality of switchingsignals, at least one of said switching signals being out-of-phase withrespect to other ones of said switching signals, a plurality of drivers,each coupled to receive one of said switching signals, and a pluralityof switching voltage converters, each coupled to receive an output fromone of said drivers and an input voltage, wherein the outputs of saidswitching voltage converters are combined to form an output voltage, andwherein said multi-phase synchronous buck regulator is implemented on amotherboard.
 15. The system of claim 14, further comprising a droopcircuit to add a droop voltage to said output voltage.
 16. The system ofclaim 15, wherein said multi-phase synchronous buck regulator is coupledto receive a plurality of input voltages, and wherein said multi-phasesynchronous buck regulator further comprises a sequence timing controlcircuit to allow proper operation of said multi-phase synchronous buckregulator regardless of the sequencing of said input voltages.
 17. Thesystem of claim 14, wherein said multi-phase synchronous buck regulatorfurther comprises an over-voltage protection circuit.
 18. The system ofclaim 14, wherein said multi-phase synchronous buck regulator isimplemented on a central processing unit chip.
 19. The system of claim18, wherein said pulse width modulator comprises a programmable,multi-phase, high performance PWM controller.
 20. The system of claim19, wherein each of said drivers comprises a high speed synchronouspower MOSFET smart driver.
 21. The system of claim 20, wherein each ofsaid switching voltage converters includes a plurality of switchingMOSFETs, and an output inductor.
 22. The system of claim 14, whereinsaid multi-phase synchronous buck regulator is implemented on aninterposer.
 23. The system of claim 22, wherein said pulse widthmodulator comprises a PWM controller.
 24. The system of claim 14,wherein the switching signals from one phase to a next phase areseparated by 90°.
 25. A system comprising a DC-to-DC regulatorcomprising: a plurality of multi-phase synchronous buck regulatormodules, wherein each of said modules includes: a pulse width modulatorto generate a plurality of switching signals, at least one of saidswitching signals being out-of-phase with respect to other ones of saidswitching signals, a plurality of drivers, each coupled to receive oneof said switching signals, a plurality of switching voltage converters,each coupled to receive an output from one of said drivers and an inputvoltage, wherein the outputs of said switching voltage converters arecombined to form an output voltage, and a current sharing circuit toinsure that the current load is shared amongst said plurality ofmulti-phase synchronous buck regulator modules, and wherein saidmulti-phase synchronous buck regulator modules are implemented on amotherboard.
 26. The system of claim 25, wherein the switching signalsfrom one phase to a next phase are separated by 90°.
 27. A DC-to-DCregulator, comprising: a multi-phase synchronous buck regulatorincluding: a pulse width modulator to generate a plurality of switchingsignals, at least one of said switching signals being out-of-phase withrespect to other ones of said switching signals, a plurality of drivers,each coupled to receive one of said switching signals, and a pluralityof switching voltage converters, each coupled to receive an output fromone of said drivers and an input voltage, wherein the outputs of saidswitching voltage converters are combined to form an output voltage. 28.The DC-to-DC regulator of claim 27 , wherein said multi-phasesynchronous buck regulator is implemented on an interposer.
 29. TheDC-to-DC regulator of claim 28 , wherein said multi-phase synchronousbuck regulator is coupled to receive a plurality of input voltages, andwherein said multi-phase synchronous buck regulator further comprises asequence timing control circuit to allow proper operation of saidmulti-phase synchronous buck regulator regardless of the sequencing ofsaid input voltages.
 30. The DC-to-DC regulator of claim 27 , furthercomprising a droop circuit to add a droop voltage to said outputvoltage.
 31. A system comprising a DC-to-DC regulator comprising: aplurality of multi-phase synchronous buck regulator modules, whereineach of said modules includes: a pulse width modulator to generate aplurality of switching signals, at least one of said switching signalsbeing out-of-phase with respect to other ones of said switching signals,a plurality of drivers, each coupled to receive one of said switchingsignals, a plurality of switching voltage converters, each coupled toreceive an output from one of said drivers and an input voltage, whereinthe outputs of said switching voltage converters are combined to form anoutput voltage, and a current sharing circuit to insure that the currentload is shared amongst said plurality of multi-phase synchronous buckregulator modules.
 32. The system of claim 31, wherein said multi-phasesynchronous buck regulator modules are implemented on an interposer. 33.A DC-to-DC regulator, comprising: a plurality of multi-phase synchronousbuck regulator modules, wherein each of said modules includes: a pulsewidth modulator to generate a plurality of switching signals, at leastone of said switching signals being out-of-phase with respect to otherones of said switching signals, a plurality of drivers, each coupled toreceive one of said switching signals, a plurality of switching voltageconverters, each coupled to receive an output from one of said driversand an input voltage, wherein the outputs of said switching voltageconverters are combined to form an output voltage, and a current sharingcircuit to insure that the current load is shared amongst said pluralityof multi-phase synchronous buck regulator modules.
 34. The DC-to-DCregulator of claim 33 , wherein said multi-phase synchronous buckregulator modules are implemented on an interposer.
 35. A systemcomprising a DC-to-DC regulator comprising: a multi-phase synchronousbuck regulator including: a pulse width modulator to generate aplurality of switching signals, at least one of said switching signalsbeing out-of-phase with respect to other ones of said switching signals,a plurality of drivers, each coupled to receive one of said switchingsignals, and a plurality of switching voltage converters, each coupledto receive an output from one of said drivers and an input voltage,wherein the outputs of said switching voltage converters are combined toform an output voltage.
 36. The system of claim 35, wherein saidmulti-phase synchronous buck regulator is coupled to receive a pluralityof input voltages, and wherein said multi-phase synchronous buckregulator further comprises a sequence timing control circuit to allowproper operation of said multi-phase synchronous buck regulatorregardless of the sequencing of said input voltages.
 37. The system ofclaim 35, wherein said multi-phase synchronous buck regulator isimplemented on an interposer.
 38. The system of claim 35, wherein saidmulti-phase synchronous buck regulator is implemented on a centralprocessing unit chip.
 39. The system of claim 35, further comprising adroop circuit to add a droop voltage to said output voltage.